SONET 2.5 Gb/s OC-48 front-end daughter board for OCDrop product.   This board uses an AMCC  chipset (S3041 / S3042 / S3045) to split the OC-48 stream into four STS-12 streams which are then supplied to the OC-Drop motherboard.  This top-side view shows the two OC-48 tranceivers, the two sets of AMCC chips, and the VXCO and PLL circuitry for providing an externally-locked transmit clock, as well as a 3.3V switching regulator.
 

Bottom view of same dual line-side OC-48 board, showing the 2.5 GHz circuitry, the Lattice FPGAs for selecting one of the four STS-12 streams, and the remainder of the transmit clock components.  The FPGAs also allow drop-insert capability of selected bytes within the SONET overhead of the full OC-48 stream.