ATM protocol analyzer card set
This is the top view of an S-bus card for a protocol analyzer that was designed to collect ATM cells, cell headers, or streams from both line sides, time-stamp them, and provide protocol decode options for the content. It uses LSI logic ATMizer chips 256K of SRAM and LANCAM chips for table lookup. To the left of the ATMizers is a UTOPIA bus connector which mates to one of several front-end daughter boards.
This is the underside of the same ATM card, showing the S-bus connector at the left, four Altera 7000 series FPGA chips and four 4M SDRAM chips with footprints for 16M parts.
Plug-in Daughter Boards
This is the dual channel SONET OC-3 optical front-end daughter board which plugs onto the ATM analyzer S-bus card above. It uses two PMC-Sierra SONET framer chips to extract the cells from the STS-3C payload and place them on the UTOPIA bus. The board also provides access to DCC overhead through the connector mounted between the two optical tranceivers.
This is the DS-3 electrical interface for the ATM protocol analyzer card. It uses two PMC Sierra SUNI-PDH chips to extract cells from the DS-3 payload. Overhead access is provided through the connector between the DS-3 jack pairs.